(a) Field of the Invention
The present invention relates to an internal-logic inspection circuit and, more particularly, to a device structure and a layout of a semiconductor device such as LSI for inspecting the logic levels of internal nodes therein with a non-contact and non-destructive technique by using a laser beam. The present invention also relates to a method for internal-logic inspection of a semiconductor device.
(b) Description of a Related Art
An internal-logic inspection technique using a laser beam is generally employed for a logical verification of internal logic in an LSI. Conventional internal-logic inspection techniques include one such as proposed in "Logic Failure Analysis of CMOS VLSI using a Laser Probe", IEEE 1984, on International Reliability Physics Symposium, pp. 69-75 by F. j. Henley.
FIGS. 1A and 1B are circuit diagram of a CMOSFET in the internal circuit of an LSI and a sectional view thereof, respectively, with reference to which the principle of the proposed technique will be described. In FIG. 1A, the CMOSFET includes a p-ch transistor and an n-ch transistor connected in series between VDD line and the ground. In FIG. 1B, each of the FETs has a source region 51 or 61 formed on a p-type silicon substrate (p-sub) 50 and connected to VDD line (high voltage source line) or ground line (low voltage source line), a drain 52 or 62 connected to an output node OUT, and a gate electrode 53 or 63 connected to an input terminal IN.
Referring to FIG. 2, the drain region 62 of the nMOSFET shown in FIG. 1B is irradiated by a laser beam for logic inspection. The laser beam is irradiated by YAG having a wavelength of 1.06 .mu.m which has a sufficient energy for exciting the p-n junction formed by the drain region 62 and the substrate 50. If the input voltage is high, the pMOSFET is OFF and the nMOSFET is ON, whereby the output node OUT assumes a low level. The laser beam irradiated onto the drain region 62 of the nMOSFET generates electron-hole pairs in the drain region 62. The electrons are drained through the channel and the source region 61 of the nMOSFET toward the ground line, whereas the positive holes are drained toward the ground line through the substrate 50 and a substrate electrode 64, which provides a reverse bias for the p-type substrate. The positive holes and electrons are then subjected to recombination in the vicinity of the substrate electrode 64, and thus current is not detected in the ground line.
Referring to FIG. 3, if the input voltage is low, the pMOSFET is ON and the nMOSFET is OFF, whereby the output node OUT assumes a high level. When the laser beam is irradiated onto the drain region 62 of the nMOSFET, electron-hole pairs are generated. The electrons thus generated are drained to VDD line through the pMOSFET, whereas positive holes are drained to the ground line through the p-type substrate 50 and the substrate electrode 64, whereby small current can be detected in the ground line by a small-range ammeter. The presence or absence of the small current I.sub.ph informs the output level of the CMOSFET at this stage. That is, if the small current is not detected, it shows a low level of the output node OUT, and if the small current is detected, it shows a high level of the output node OUT.
The conventional logic inspection techniques include one described in Patent Publication JP-A-5-21739, wherein a node connecting an output of a transistor element and an input of a succeeding transistor element is electrically connected to a diffused region electrically separated from other diffused regions and having a conductivity type opposite to the conductivity type of the semiconductor substrate, and the node thus formed is irradiated by a laser beam for logic inspection thereof.
FIG. 4 shows an example of the irradiation node described in the Patent Publication, wherein an n-type diffused region 65 is formed as the irradiation node in the surface region of a p-type substrate 50 and connected to an interconnect 66 connecting the output node OUT of an internal CMOSFET and an input node of another internal circuit. Adjacent to the irradiation node 65, a substrate electrode 64 is provided and connected to the ground line for electric separation by a reverse bias voltage.
Referring to FIG. 5, the irradiation node 65 shown in FIG. 4 is irradiated by a laser beam for internal logic inspection. If the input terminal of the CMOSFET is applied with a high level to turn OFF the pMOSFET and turn ON the nMOSFET, the positive holes and electrons generated by the laser beam as electron-hole pairs are drained through the interconnect or the substrate 50 to the ground line, wherein the electrons and positive holes are recombined. Thus, current I.sub.ph flowing to the VDD line is not detected in the case of a high level of the input signal.
Referring to FIG. 6, the irradiation node 65 shown in FIG. 4 is irradiated by a laser beam in the case of a low level of the input signal for the CMOSFET. In this case, the electrons are drained to VDD line through the p-ch transistor, whereas the positive holes are drained to the ground line through the substrate electrode 64. Thus, current Iph flowing to the VDD line is detected in the case of a low level of the input signal.
In the mean time, a situation has arisen in the state of art semiconductor devices, wherein the delay time caused by the line length is not negligible compared to the delay time in the transistor elements due to the reduction in the transistor dimensions.
FIG. 7 shows the relationship between the line length and the propagation delay generated by the line length, the relationship being specified by delay standards D1 and D2 which depend on the device dimensions, i.e., D1 corresponds to a larger transistor dimension and D2 corresponds to a smaller transistor dimension. As shown in the drawing, in the range L1 of the line length larger than a specified length LT, the propagation delay denoted by G1 and caused by the line length dominates in the signal delay with respect to the delay time D2 caused by the parasitic capacitance or parasitic resistance of the device elements in next generations of the semiconductor device having smaller device dimensions. Thus, it is desired that the circuit design reduce the line length for a higher operational speed of the semiconductor devices.
In a multi-layered interconnect structure in the semiconductor devices, there are variety of improvements wherein the parasitic capacitances of the signal lines are reduced by using the top interconnect layers as electrode lines, wherein resistance to noise in the supply voltage is improved by making the power source lines to cover almost the whole area for the semiconductor chip, and wherein a further high-performance semiconductor devices are achieved by an increase in the number of layers up to five or above to thereby reduce the potential difference in the signal lines.
In the improvements as described above, the internal-logic inspection technique using a laser beam has a problem in that the area for irradiating the laser beam is extremely limited due to the overlying interconnect layers covering almost whole area of the chip. This results in that the drain of the MOSFET cannot be irradiated by the laser beam in the first conventional technique, and results in that the irradiation node in the second conventional technique is located in the outer periphery of the semiconductor chip, which in turn causes a larger line length or larger transmission delay and degrades the electric characteristics of the semiconductor devices.